Manikandan Palanichamy

2016-10

Manikandan Palanichamy, KW Lam, JCW Pang, KH Loo, YM Lai, SY Chau, “LED Growth Light with Flexible Photoperiods and Programmable Light Output Intensity”, Proceedings of 2016 International Conference on Plant Factory (ICPF'2016), Republic of Korea, 12-14 October 2016

ABSTRACT: Water, food and energy are going to be a big challenge in the future. As a result of understanding this fact that the world cannot only depend on conventional agriculture, it is moving towards soil-free, sunlight-free, and pesticides-free self-sustainable indoor cultivation systems. Indoor cultivation works without changing anything about the genetics of seeds but just by optimizing the environment where plants are growing, so called a controlled environment. Researchers, engineers and programmers are helping to rebuild the global agriculture industry by providing a path of technological opportunities for people of modest means to become farmers. Thus, light emitting diode (LED) lighting systems were introduced to replace sunlight in indoor cultivation systems. When LEDs are applied in such high power application as multiple parallel strings it has a current deviation issue that leads to short life-time, uncontrolled light intensity, and additional energy consumption of LEDs. This paper presents an active current balance approach by using switch mode current converters to regulate and balance the current in each LED string with flexible photoperiod and light intensity levels. We also improved the current deviation deficiency from 32.7-28.5% to 6.5% in multi-parallel LED strings system.

2016-07

Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, and Bruno Rouzeyre,"Hardware Trust Through Layout Filling: A HT Prevention Technic”, IEEE Proc. ISVLSI 2016, USA, pp. 254-259

ABSTRACT: The insertion of malicious alterations to a circuit, referred to as Hardware Trojans, is a threat considered more and more seriously during the last years. Numerous methods have been proposed in the literature to detect the presence of such alterations. More recently, Design-for-Hardware-Trust (DfHT) methods have been proposed, that enhance the design of the circuit in order to incorporate features that can either prevent the insertion of a HT or that can help detection methods. This paper focuses on a HT prevention technique that aims at creating a layout without filler cells, which are assumed to provide a great opportunity for HT insertion, in order to make the insertion of a HT in a layout as difficult as possible.

2016-09

Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, and Bruno Rouzeyre, "Duplication-based Concurrent Detection of HTs in Integrated Circuits”, IEEE Proc. DATE 2016 (TRUDEVICE’16), Germany, pp. 122-128.

ABSTRACT: Outsourcing the fabrication process to low-cost locations has become a major trend in the Integrated Circuits (ICs) industry in the last decade. This trend raises the question about untrusted foundries in which an adversary can tamper with the circuit by inserting a malicious behavior in the ICs, referred to as Hardware Trojans (HTs). The serious impact of HTs in security applications and global economy brings extreme importance to detection as well as prevention techniques. In this paper, we introduce the idea of hardware modified dual modular redundancy (MODMOR): a prevention technique that aims at making the insertion of a stealthy HT more difficult, and at detecting it at run-time.

2015-08

Palanichamy Manikandan, Papa-sidy Ba, Sophie Dupuis, Marie-Lise Flottes , Giorgio Di Natale, Bruno Rouzeyre, “Hardware Trojan prevention using layout level design approach ”, IEEE Proc., The 22nd European conference on circuit theory and design, ECCTD2015, pp. 1-4, Aug. 2015, Norway.

ABSTRACT: Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention technique through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.

2015-09

Palanichamy Manikandan, Papa-sidy Ba, Sophie Dupuis, Marie-Lise Flottes , Giorgio Di Natale, Bruno Rouzeyre, “Run-time dual modular HT detection in integrated circuits ”, Trustworthy Manufacturing and Utilization of secure devices 2015, Sep. 17, Saint-Malo, France (ICT COST).

2015-12

P. Manikandan, Bjorn B. Larsen and M. Areef, “Selective Algorithms for Programmable Built-in Self-Test and Self-Diagnosis for Embedded SRAMs”, Published in ASP Journal of low power electronics, Vol. 11, Number 4, Dec. 2015.

ABSTRACT: Memories are one of the most universal cores that are embedded into almost all system on chips (SoCs). Finding cost effective test solution for embedded memories is paramount. Industries are still improving the existing low-cost memory test solutions which can support current technologies and advanced SoC architectures. This paper presents a programmable built-in self-diagnosis (PBISD) methodology with self-test for embedded SRAMs. The BISD logic adapts the test controller with micro code encoding technique in order to control the test operation sequences for fault detection. It also encompasses a diagnosis array in order to locate the fault sites. The macro codes are used to select any of seven MARCH algorithms and detect different faults of the memory under test (MUT). This BISD supports the test, diagnosis and normal operation modes. The experimental results show that this work gives 17–47% improved area overhead and 16–41% enhanced speed compared to three published results.

2011-11

P. Manikandan, Bjorn B. Larsen and M. Areef, “Design of embedded TCAM based longest prefix match search engine”, Elsevier International journal on Microprocessors and Microsystems - Design and Verification of Complex Digital Systems, Volume 35, Issue 8, November 2011, Pages 659-667.

ABSTRACT: The content addressable memory (CAM) based solutions are very useful in network applications due to its high-speed parallel search mechanism. This paper presents a novel Ternary CAM (TCAM) based NAND Pseudo CMOS-Longest Prefix Match (NPC-LPM) search engine. The proposed system provides a simple hardware-based solution using novel 11T TCAM cell structures and NPC word line technique, for network routers. The experiments were performed on 256 × 128 NPC-LPM system under 0.13 μm technology. The simulation result shows that the proposed design provides low power dissipation of 5.78 mW and high search speed of 315 MSearches/s under 1.3 V supply voltage. The presented NPC-LPM system meets the speed requirement of Optical Carrier (OC) 3072 with line-rate of 160 Gb/s in Ethernet networking and IPv6 protocol. The experimental results also show that the proposed system improves power-performance by 65%.

2013-09

Type: IEEE Proceedings, Published in IEEE Proceedings, IEEE International Conference EWDTS-2013, pp 1-6, September 2013. ISBN: 978-1-4799-2095-2, Co-author(s): B. A. A Abbas, V. I. Hahanov, E. I. Litvinova, S. Dementiev

ABSTRACT: The results of studies concerning the models and methods of quantum diagnosis of digital systems, qubit fault simulation and analysis of fault-free behavior, as well as repair of faulty primitives, are presented.

2011-09

Type: IEEE Proceedings, Published in IEEE International Conference EWDTS-2011, pp 1-6, September 2011, Ukraine ISBN: 978-1-4577-

1957-8. Co-author(s): Einar J. Aas, Bjørn B. Larsen and M. Areef. 

ABSTRACT: This paper presents a programmable built-in self-test (PBIST) methodology for embedded SRAMs. The BIST Logic adapts the test controller with micro code encoding technique in order to control test operation sequences. The macro codes are used to select any of seven MARCH algorithms, and detect, different faults of the memory under test (MUT). This BIST supports both the test and normal operation modes. The experimental results show that this work gives 17-47% improved area overhead and 16-41% enhanced speed compared to Three published results.

2011-09

Type: IEEE Proceedings, Published in IEEE International Conference DSD-2011, ISBN: 978-0-7695-4494-6. Degree: Ph.D. Co-author(s): Einar J. Aas and Bjørn B. Larsen

ABSTRACT: This paper presents an enhanced path delay fault, simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of, ISCAS’85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental results show that the modified path selection and simulation algorithm provides good fault coverage and 20% improved simulation time as an average speed-up factor.

2010-09

Type: IEEE Proceedings, Published in IEEE International Conference DSD-2010, ISBN: 978-1-4244-7839-2. Co-author(s): Einar J. Aas and Bjørn B. Larsen

ABSTRACT: Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using a minimum number of test patterns. This paper proposes a test method to detect critical path delay faults in CAM systems using a newly proposed low power TCAM cell structure. The proposed complement bit walk (CBW) algorithms are using low time complexity such as 3m+n and 2m+2n operations. The fault simulation of the given TCAM system provides 100% fault coverage for the write, search and pseudo logic faults.

2010-11

Type: IEEE Proceedings, Published in IEEE International Conference TENCON-2010, 1150-1155, November 2010, Japan. ISBN: 978-1-4244-6889-8, Co-author(s): Einar J. Aas and Bjørn B. Larsen

ABSTRACT: Embedded content addressable memories are very useful in many applications such as network switch, IP filters and longest prefix match search engine, where high speed search is essential. This makes it a necessity to find an efficient self-test methodology in order to measure its internal worst-case search speed. This paper presents a pseudo CMOS logic (PC) based ternary content addressable memory (TCAM) system using novel 11T cell structure in addition with embedded built-in self-test approach. This approach contributes in building an efficient and flexible CAM system with an emphasis on its maximum critical search speed measurement under worst case operation. The experimental results show that the presented BIST methodology is more effective and provides improved search delay measurement such as 1.72ns and a power performance metric such as 0.202 fJ/bits/Searchers in the 256×128 PC-TCAM system.

2010-09

Type: IEEE Proceedings, Published in IEEE International Conference EWDTS-2010, 110-115, September 2010, Russia. ISBN: 978-1-4244-9555-9. Degree: Ph.D. Co-author(s): Einar J. Aas and Bjørn B. Larsen

ABSTRACT: This paper presents SIC based test stimuli with, Arithmetic Built in Self-Test (ABIST) concept in order to detect the path delay faults. The presented generator with ABIST stimuli is quite useful for detecting the K-longest path-delay faults of the microprocessor. This paper extends the work of Ø. Gjermundnes [1], [2] and presents its application and validation to the Intel 8051 microprocessor. The experimental results of this, work with the given test case microprocessor allows us to validate the proposed test method is effective by the obtained fault coverage.

2010-12

Type: IEEE Proceedings Title: Testing of Embedded Content Addressable Memories Publishing: IEEE International Conference ISED-2010, 113-118, December 2010, India. ISBN: 978-1-4244-8979-4. Co-author(s): Einar J. Aas and Bjørn B. Larsen

2009-05

Type: ACM Proceedings, Published in ACM Proceedings, GLSVLSI-2009, 57-62, May 2009, Boston-USA. ISBN: 978-1-60558-522-2. Co-author(s): Einar J. Aas and Bjørn B. Larsen

ABSTRACT: This paper presents novel cell structures for fully parallel static type binary content addressable memory (BCAM) with low power and high flexibility. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the Word match line (ML) structure of low power BCAM employs Static, pseudo CMOS (SPC) logic. HSPICE simulations for 32×32 and 128×32 BCAM systems were performed under 0.18 μm Technology for different cell structures. The result shows that the proposed, design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns @ 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM show that the proposed BCAM cell reduces power dissipation by 76% and improves search speed by 65%.

2006-12

Type: IEEE Proceedings, Published in IEEE International Conference APCCAS-2006, 4-8 December, Singapore. ISBN: 1-4244-0387-1, Co-author(s): B.D. Liu, L. Y. Chiou, G. Sundar and C. R. Mandal. IEEE Best Paper Award

ABSTRACT: We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

2010-09

Type: IEEE Workshop report, P. Manikandan, “IEEE Standards and Benchmarks in electronics engineering”, IEEE National level Student Conference, Sep. 14 2010, NTNU, IEEE Region 8 of Europe, Norway.

2011-04

Type: IEEE workshop report, P. Manikandan, “Role of IEEE in emerging electronics and its research: An overview”, 1st Inter European Workshop (IEW'2011), April 28, 2011, NTNU, IEEE Region 8 of Europe, Norway.

2006-01

Type: International Meeting on Microsensors and Microsystems, Title: Design and Implementation of VLSI SoC for Remote Sensing Applications, Publishing: National Science Council of Taiwan, 2nd International Meeting on Microsensors and Microsystems, pp 168-169, Jan 15-18, 2006, Taiwan. Co-author (s): BD Liu, VKP Tripathi and G. Sundar

2005-06

Type: IEEE VLSI Society of India Conference proceedings Title: “A Design Technique for the Implementation of Asynchronous ALUs Publishing: Proc. of VEDAS-2005, June 1-2,2005, India. Co-author (s): G. Sundar and CR Mandal.